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LV5213LP
Serial Data Transfer Timing Conditions
Parameter
Cycle time
Data setup time
Symbol
tcy1
ts0
Conditions
SCLK clock period
The CS setup time from the SLCK rising edge
min
330
150
typ
max
unit
nS
nS
ts1
The SDATA setup time from the SLCK rising edge
100
nS
Data hold time
Pulse width
th0
th1
tw1L
tw1H
tw2L
The CS hold time from the SLCK falling edge
The SDATA hold time from the SCLK rising edge
SCLK low period pulse width
SCLK high period pulse width
CS low period pulse width
300
100
150
150
1.0
nS
nS
nS
nS
μ S
Data length:
Clock frequency:
16bits
Up to 2MHz
After 16 clock cycles have been input with CS at the high level, SDATA is acquired on the fall of CS.
Note: SDATA will not be acquired if 15 or fewer clock cycles were input during the CS high-level period. If 17 or more
clock cycles are input, the SDATA for the first 16 cycles are acquired and the SDATA following those 16 cycles is
ignored.
Power Supply Application
1. Either bring up VCC and VDD at the same time, or bring up VCC first then VDD.
2. Then, set the serial data. (After the serial data has been set, a period of about 2μs is required as the startup time for
the IC internal circuits.)
3. Finally, clear the STBY pin states.
No.A0183-8/10
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